Generates code for the selected processor's instruction set.
Generates code using the floating point capabilities of the selected processor or software floating point code if the processor has no floating point support.
Rejects any use of floating point variables or constants in C, C++, or Pascal. Equivalent to the -fnone build-time option.
Generate software floating point emulation code, regardless of the capabilities of the selected processor. Libraries built for software will also be used. Equivalent to the -fsoft build-time option.
Uses hardware floating point for single precision, but software floating point for double precision (when this mode is supported in the selected processor). The compiler uses different libraries instead of the default. Equivalent to the -fsingle build-time option.
RH32 always uses the Embedded Calling Sequence, which is the default. Therefore this item should be kept as "Default" for RH32 (equivalent to the -embedded_calling_sequence command line option). Selecting "Workstation" (equivalent to the -workstation_calling_sequence command line option) would have undefined effect on the code generation.
Select for which Floating Point Unit the floating point instructions are generated. When the FPU number is n, the compiler will append n to every floating point instructions generated when appropriate. The default FPU number is 0. Equivalent to the -fpu=n option.
The following are descriptions of the items in the MIPS window.
Generates position independent code. Equivalent to the -pic PIC option.
Generates position independent data. Equivalent to the -pid PID option.
Generates code that does not use the PIC base register. Code compiled with this option is absolutely addressed, but can be safely linked with code compiled with the position independent code or position independent data options.
MIPS Assembler Compatible Output
Produces assembly language code for the MIPS native assembler. By default, code is produced for the Green Hills assembler.
Generates code with little endian byte order. The least significant byte of an integer appears at the lowest address. This is the default with native compilers on the DEC station and is also used for embedded development. Equivalent to the -littleendian command line option.
Enables the MIPS-16 ISA. Equivalent to the -mips16 command line option.
Link in the MIPS-16-specific runtime libraries (prebuilt with MIPS-16 enabled) by default, when the MIPS-16 instruction set is enabled. If the MIPS-16 ISA is not enabled, clicking this button will have no effect. Equivalent to the -mips16_lib command line option
Enables the 64-bit mode. In this mode, all registers are 64-bit wide, and 64-bit integers and arithmetical are supported (via the long long type). However, pointers and addresses are still 32 bits. This option is not available with all processors. Equivalent to the -64bit command line option.
Enables the far function call mode. All functions are called via the jalr instruction instead of the jal instruction by first loading the address of the function into a temporary register. This allows the functions called to be in any address within the range of 32 bits. Equivalent to the -farcalls command line option.
Always generates the inlined prologue/epilogue code that saves and restores the permanent registers in/from the stack of a function. If this option is not turned on, then the compiler will choose for each function to generate the prologue/epilogue code either inlined or offlined (when in Software Floating Point mode, and not with -ga nor -G), depending on which is better for code size when the # of registers to be saved/restored are more than 2.
Note: An offline prologue/epilogue is a function call to a library routine __savegN that saves registers $16 to $N, or __restgN that restored registers $16 up to $N, respectively. These routines exist in indarch.a.
Multiple Near Code Regions (MIPS-X only)
Generates code in 'multiple near code region mode'. This is used to create multiple code regions in memory. Code in each region is accessible via an offset from a base register whose initial value is determined during link time by specifying the -initreg linker option. This feature is available for MIPS-X only. See your Development Guide for more information.
Small Data or Zero Data Threshold
Specifies a size in bytes to determine which data objects appear in the Small or Zero Data Areas. By default, objects less than 8 bytes are placed in Small Data Area, and no objects are placed in Zero Data Area. Equivalent to the -sda= and -zda= special data area options.
Puts variables smaller than threshold into the Data Area.
Allocates an area of memory to hold data objects smaller than the Small Data Threshold and references objects in that area using r4 as the base pointer register. Equivalent to the -sda Small Data Area option.
Allocates an area of memory to hold data objects smaller than the Zero Data Threshold and references objects in that area using r0 as the base pointer register. This improves program size and speed because addressing an object via the Small/Zero data area base register uses fewer instructions. The total size of the Small/Zero data area is limited to 64k; large applications may not be able to take advantage of this feature. Equivalent to the -zda special data area option.