Instruction
|
Description
|
Operands
|
Opcode(hex)
|
---|
abs
|
absolute value
|
reg1
|
01e0
|
addc
|
unsigned add with carry
|
reg1,reg2
|
0600
|
addi
|
unsigned add with immediate
|
reg1,imm5
|
2000
|
addu
|
unsigned add
|
reg1,reg2
|
1c00
|
and
|
logical AND
|
reg1,reg2
|
1600
|
andi
|
logical AND with immediate
|
reg1,imm5
|
2e00
|
andn
|
logical AND NOT
|
reg1,reg2
|
1f00
|
asr
|
arithmetic shift right
|
reg1,reg2
|
1a00
|
asrc
|
arithmetic shift right by 1 bit
|
reg1
|
3a00
|
asri
|
arithmetic shift right immediate
|
reg1,imm5
|
3a00
|
bclri
|
bit clear immediate
|
reg1,imm5
|
3000
|
bf
|
branch if false
|
disp11
|
e800
|
bgeni
|
bit generate immediate
|
reg1,imm5
|
3200
|
bgenr
|
bit generate register
|
reg1,reg2
|
1300
|
bkpt
|
breakpoint
|
-
|
0000
|
bmaski
|
bit mask generate immediate
|
reg1,imm5
|
2c00
|
br
|
unconditional branch
|
disp11
|
f000
|
brev
|
bit reverse
|
reg1
|
00f0
|
bseti
|
bit set immediate
|
reg1,imm5
|
3400
|
bsr
|
branch to subroutine
|
disp11
|
f800
|
bt
|
branch if true
|
disp11
|
e000
|
btsti
|
bit test immediate
|
reg1,imm5
|
3600
|
clrf
|
clear if condition false
|
reg1
|
01d0
|
clrt
|
clear if condition true
|
reg1
|
01c0
|
cmphs
|
compare for higher or same
|
reg1,reg2
|
0c00
|
cmplt
|
compare for less than
|
reg1,reg2
|
0d00
|
cmplti
|
compare with immediate for less than
|
reg1,imm5
|
2200
|
cmpne
|
compare for not equal
|
reg1,reg2
|
0f00
|
cmpnei
|
compare with immediate for not equal
|
reg1,imm5
|
2a00
|
decf
|
decrement if condition false
|
reg1
|
0090
|
decgt
|
decrement and compare greater than
|
reg1
|
01a0
|
declt
|
decrement and compare less than
|
reg1
|
0180
|
decne
|
decrement and compare not equal
|
reg1
|
01b0
|
dect
|
decrement if condition true
|
reg1
|
0080
|
divs
|
signed divide
|
reg1,r1
|
3210
|
divu
|
unsigned divide
|
reg1,r1
|
2c10
|
doze
|
enter doze mode
|
-
|
0006
|
ff1
|
find first one
|
reg1
|
00e0
|
incf
|
increment if condition false
|
reg1
|
00b0
|
inct
|
increment if condition true
|
reg1
|
00a0
|
ixh
|
index halfword
|
reg1,reg2
|
1d00
|
ixw
|
index word
|
reg1,reg2
|
1500
|
jmp
|
jump
|
reg1
|
00c0
|
jmpi
|
jump indirect
|
[disp8]
|
7000
|
jsr
|
jump to subroutine
|
reg1
|
00d0
|
jsri
|
jump to subroutine indirect
|
[disp8]
|
7f00
|
ld.b
|
load unsigned byte
|
reg1,(reg2,disp4)
|
a000
|
ld.h
|
load unsigned halfword
|
reg1,(reg2,disp4)
|
c000
|
ld.w
|
load word
|
reg1,(reg2,disp4)
|
8000
|
ldm
|
load multiple registers
|
reg1-r15,(r0)
|
0060
|
ldq
|
load register quadrant
|
r4-r7,(reg1)
|
0040
|
loopt
|
decrement and loop
|
reg1,disp4
|
0400
|
lrw
|
load PC-relative word
|
reg1,[disp8]
|
7000
|
lsl
|
logical shift left
|
reg1,reg2
|
1b00
|
lslc
|
logical shift left by 1 bit
|
reg1
|
3c00
|
lsli
|
logical shift left immediate
|
reg1,imm5
|
3c00
|
lsr
|
logical shift right
|
reg1,reg2
|
0b00
|
lsrc
|
logical shift right by 1 bit
|
reg1
|
3e00
|
lsri
|
logical shift right immediate
|
reg1,imm5
|
3e00
|
mfcr
|
move from control register
|
reg1,creg2
|
1000
|
mov
|
logical move
|
reg1,reg2
|
1200
|
movf
|
move if condition false
|
reg1,reg2
|
0a00
|
movi
|
move immediate
|
reg1,imm7
|
6000
|
movt
|
move if condition true
|
reg1,reg2
|
0200
|
mtcr
|
move to control register
|
reg1,creg2
|
1800
|
mult
|
multiply
|
reg1,reg2
|
0300
|
mvc
|
move carry bit to register
|
reg1
|
0020
|
mvcv
|
move inverted carry bit to register
|
reg1
|
0030
|
not
|
logical NOT
|
reg1
|
01f0
|
or
|
logical OR
|
reg1,reg2
|
1e00
|
rfi
|
return from fast interrupt
|
-
|
0003
|
rotli
|
rotate left immediate
|
reg1,imm5
|
3800
|
rsub
|
reverse subtract
|
reg1,reg2
|
1400
|
rsubi
|
reverse subtract with immediate
|
reg1,imm5
|
2800
|
rte
|
return from exception
|
-
|
0002
|
sextb
|
sign extend byte
|
reg1
|
0150
|
sexth
|
sign extend halfword
|
reg1
|
0170
|
st.b
|
store byte
|
reg1,(reg2,disp4)
|
b000
|
st.h
|
store halfword
|
reg1,(reg2,disp4)
|
d000
|
st.w
|
store word
|
reg1,(reg2,disp4)
|
9000
|
stm
|
store multiple registers
|
reg1-r15,(r0)
|
0070
|
stop
|
enter stop mode
|
-
|
0004
|
stq
|
store register quadrant
|
r4-r7,(reg1)
|
0050
|
subc
|
unsigned subtract with carry
|
reg1,reg2
|
0700
|
subi
|
unsigned subtract with immediate
|
reg1,imm5
|
2200
|
subu
|
unsigned subtract
|
reg1,reg2
|
0500
|
sync
|
synchronize CPU
|
-
|
0001
|
trap
|
trap to operating system
|
imm2
|
0004
|
tst
|
test with zero
|
reg1,reg2
|
0e00
|
tstnbz
|
test for no byte equal to zero
|
reg1
|
0190
|
wait
|
wait for interrupt
|
-
|
0005
|
xor
|
logical exclusive OR
|
reg1,reg2
|
1700
|
xsr
|
extended shift right
|
reg1
|
3800
|
xtrb0
|
extract high order byte
|
r1,reg2
|
0130
|
xtrb1
|
extract byte 1
|
r1,reg2
|
0120
|
xtrb2
|
extract byte 2
|
r1,reg2
|
0110
|
xtrb3
|
extract low order byte
|
r1,reg2
|
0100
|
zextb
|
zero extend byte
|
reg1
|
0140
|
zexth
|
zero extend halfword
|
reg1
|
0160
|