All the addressing modes offered by the MCore processor are supported, and are summarized below:
reg1, reg2 are general purpose registers
imm5 is an unsigned 5-bit value
imm7 is an unsigned 7-bit value
disp4 is a signed or unsigned 4-bit displacement value
disp8 is an unsigned 8-bit displacement value
disp11 is a signed 11-bit displacement value
Each of these addressing modes is explained below.
Every MCore instruction is two bytes (16 bits), including those instructions containing immediate data.
In line with the RISC architecture, there are relatively few instructions and usually few addressing modes which apply to any given one. Also, a given addressing mode applies to the instruction as a whole (in contrast to some architectures which allow different addressing modes to be specified for each operand). The result is very quick and easy instruction decoding, so the lack of complex instructions and addressing modes is more than compensated for by the attendant increase in performance.
The values in the example boxes are all in hexadecimal, except that xx means "don't care what value is present". 32-bit values are written as four 8-bit bytes.
r2: DE AD C0 DE
r3: xx xx xx xx
DEADB0AC: xx xx xx xx
DEADB0B0: C0 1D BE EF
DEADB0B4: xx xx xx xx
This indicates that register r2 holds the value 0xDEADC0DE, we do not care what value r3 holds (it holds arbitrary data), the four bytes of memory starting at address 0xdeadb0b0 hold the value 0xC01DBEEF, and the four-byte words above and below each hold arbitrary data.
These instructions do not take any arguments.
rts
These instructions use the same register as the source and destination.
abs r1
This computes the absolute value of the contents of register r1 and stores the result in register r1.
These instructions have two register fields to specify one or two source registers and one destination register for the instruction.
add r2,r3
This adds the contents of register r3 to register r2 and stores the result in register r2.
mov r2,r14
This copies the contents of register r14 to register r2. r14 remains unchanged.
This addressing mode has a 5-bit immediate field as the first source operand while one register field specifies both the second source operand and the destination.
sub r0,16
This subtracts 16 from the value in register r0 and stores the result back in r0.
The movi instruction has a 7-bit immediate field as a source operand and a register field as the destination.
movi r4,100
This stores the value 100 in register r4.
These instructions copy data between the general registers (r0-r15) and the control registers (cr0 to cr31).
mfcr r2,cr1
This copies the contents of control register cr1 to general register r2.
mtcr r3,cr0
This copies the contents of general register r3 to control register cr0.
This addressing mode adds the contents of register reg1 to the scaled unsigned immediate disp4 to form an address. The ld instructions load the data at that address to the register reg2. The st instructions store the contents of register reg2 to that address.
ld.w r3,(r0,16)
This copies to register r3 the 32-bit data at the memory address calculated by adding 16 to the contents of register r0. The immediate value 16 must be a multiple of 4 because this is a 4-byte load instruction.
This addressing mode specifies a contiguous set of registers to transfer to or from the memory location pointed to by the contents of register reg1.
stm r12-r15,(r0)
This stores registers r12, r13, r14, and r15 in ascending memory locations starting at the address stored in register r0.
This addressing mode uses a 32-bit word pointed to by a PC-relative address as a source operand. The address is computed by adding the unsigned 8-bit immediate field, scaled by four, to the value of PC+2. The lower two bits of this address are then masked to 00.
lrw r1,[100]
This loads 32-bit word at address PC+2+100 and stores the result in register r1.
This addressing mode computes a branch address by adding the sign-extended displacement value disp11, scaled by two, to the address PC+2.
bt -16
This instruction branches to the address PC+2-16 if the condition code bit is set.
The loopt instruction uses this addressing mode to specify a register to store a loop counter and a branch address formed by subtracting the 4-bit displacement, scaled by two, from the address PC+2.
loopt r2,-8
This instruction branches to the address PC+2-8 if the loop counter in register r2 is not zero.